Communications systems and computer systems have components that operate at different speeds. Typically, these systems use Phase-Locked Loops (PLLs) for synchronization of their components. A PLL generally includes a phase detector, a loop filter, a Voltage-Controlled Oscillator (VCO), and a loop divider. The phase detector provides a phase detect output signal that indicates the phase difference between a loop clock signal and a reference clock signal. The phase detector provides the phase detect output signal to an input of the loop filter, which in turn provides a filtered signal to the VCO. The filtered signal indicates the length of time that the two clock signals are out of phase. The VCO provides a clock output signal having a desired frequency. The clock output signal is divided by the loop divider to provide the loop clock signal.
In a portable computer system, power is conserved by reducing the clock rates of some of its components. For example, in a computer system designed to operate at 66 MegaHertz (MHz), some components, such as timing clocks, can be maintained at a lower clock rate of 32 MHz when the computer is not in use. Problems in synchronization can occur if the output frequency of the PLL changes from a higher to a lower frequency before downstream components are ready to accept the altered output frequency. In one example, a downstream component that requires a delay on the order of milliseconds before receiving the changed input frequency may be coupled to a PLL that switches from one frequency to another within a few microseconds. The timing difference can lead to race conditions, code execution failure, improper turning on or turning off of buses, etc.
One method for delaying the change in output frequency of the PLL is to delay the filtered signal transmitted to the VCO from the loop filter. This can be done by increasing the capacitance of the loop filter. To achieve a timing delay on the order of milliseconds, one or more microfarad-sized capacitors are needed. In the field of monolithic integrated circuits, where space on a chip is limited, the addition of one or more microfarad-sized capacitors restricts a circuit designer's options with regard to other components. It also increases the cost of the chip. Another disadvantage of this approach, is that modifying components of the PLL can adversely affect the gain and the operating bandwidth of the PLL, resulting in signal jitter at the output of the PLL.
Accordingly, it would be advantageous to have a PLL and method for altering the time it takes for the PLL to transition from one frequency to another. It would be of further advantage for the PLL to be area and cost efficient.